The invention relates to a circuit arrangement for deriving digital color signals from an analog television signal with an analog/digital converter, which forms from the analog television signal a digital television signal, which comprises a sequence of discrete-amplitude samples of the analog television signal with a repetition frequency determined by a clock signal that corresponds to a whole multiple of the line frequency of the television signal, a demodulator which forms the digital color signals by multiplication of the digital television signal by at least a digital demodulation signal, a first phase detector which derives from certain digital color signals a color signal which is a measure of the phase positions of the digital color signals relative to the demodulation signals, a first phase calculator which delivers a first control signal that consists of a sequence of values with a repetition frequency determined by the clock signal and whereby the difference between every two consecutive values is adjusted by the color phase signal, and a signal generator which forms from the control signal the demodulation signal or signals, and a reference circuit which comprises a reference signal source, a phase detector that generates a reference phase signal, and a second phase calculator that delivers a second control signal consisting of a sequence of signal values, whereby the difference between every two consecutive signal values is adjusted by the reference phase signal, and which supplies the reference phase signal to the first phase calculator for supplementary adjustment of the difference between two consecutive values of the first control signal.
A circuit arrangement of this type is known from European Patent Application No. 111 981. The circuit arrangement therein described comprises a phase calculator which is supplied with a clock signal whose frequency corresponds to a whole multiple of the line frequency of the television signal and which delivers a control signal. This control signal consists of a sequence of values of discrete amplitude whose repetition frequency corresponds to the frequency of the clock signal. The values of the control signal address in a read-only memory (signal generator) samples or a sinusoidal and a cosinusoidal signal which are respectively delivered at an output with a repetition frequency corresponding to the frequency of the clock signal. The frequency of the sinusoidal and of the cosinusoidal signal is thereby equal to the frequency of the color synchronization signal in the television signal. The analog television sigal is sampled in an analog/digital converter with the frequency of the clock signal and thereby converted into a pulsed sequence of discrete-amplitude digital samples. This digital television signal is multiplied in two multipliers by the sinusoidal and by the cosinusoidal signal, respectively, from the read-only memory. The digital color difference signals thereby formed are fed to a phase detector which generates a color phase signal. This is fed to the phase calculator for correcting the difference between two consecutive values of the control signal sent to the signal generator.
Fixing the clock frequency at a whole multiple of the line frequency of the television signal instead of fixing it at a whole multiple of the frequency of the color synchronization signal has the advantage that the time sequence of the samples of the television signal is directly adapted to its line, field and frame structure. This considerably simplifies the use of digital picture memories and improves the resultant picture quality. It also simplifies the processing of television signals of different standards.
A phase calculator in accordance with the prior art comprises in the simplest case a modulo adder with two inputs and one output, which is connected to an input of a register whose output is looped back to one of the inputs of the modulo adder. Via the second input a digital signal is supplied to the modulo adder whose value is also described as an increment. The modulo adder is further supplied with a clock signal. In each period of this clock signal the values of the signals applied to the inputs of the modulo adder are added together and the resultant sum signal is fed via the output of the modulo adder to the register, where it is stored. The value stored in the register during a period of the clock signal is fed to the first input of the modulo adder, and in the next period of the clock signal it is linked with the increment to form a new sum signal.
Such a phase calculator thus essentially constitutes an accumulator arrangement, which accumulates the increment with the frequency of the clock signal. The increment thereby forms the difference between two consecutive values of the sum signal and thus of the signal delivered at the output of the register. During accumulation the sum signal is thus increased in steps from an initial value with the frequency of the clock signal until a certain value is exceeded, at which point the accumulation begins again starting with the residual value. The sequence of the values of the signal delivered from the phase locked loop at the output of the register thus forms a discrete-time periodic signal with a frequency that depends on the frequency of the clock signal and on the increment. It is thus on the one hand possible to adjust with the increment the frequency of the signal delivered from the phase calculator, but on the other hand flucuations in the frequency of the clock signal, which may be caused in particular by variations in the line frequency of the television signal, can become troublesome. Such fluctuations typically occur in television signals obtained from video recorders and similar apparatus. Via the sinusoidal and cosinusoidal signals used respectively for demodulating the television signal to obtain the chrominance signal, fluctuations occur in the color difference signals that give rise to troublesome color interference in the television picture. It appears that the television picture is much more sensitive to color distortions caused by a deviation in the frequency of the clock signal than to a deviation of the line frequency corresponding to this deviation in the frequency of the clock signal.
In the known circuit arrangement a reference circuit has therefore been added that generates a reference phase signal which is fed to the first phase calculator in order to compensate for clock signal frequency fluctuations caused by line frequency fluctuations. With the aid of the second phase calculator the reference circuit generates in addition the clock signal having the line frequency. The reference phase signal serves as an increment of the second phase calculator, which accumulates the increment with the frequency of a reference clock signal generated by the reference signal source. In a converter which follows the second phase calculator and which forms a sawtooth signal from a squarewave signal, the said converter comprising at least a D/A converter, the clock signal is formed which is also fed via a frequency divider to the second phase detector. The second phase detector, which is also supplied with line sync pulses, generates therefrom the reference phase signal. Since the frequency of the reference signal source is much higher than the clock signal frequency, fast and therefore costly digital building blocks and also fast D/A converter are required for the stages operating at the frequency of the reference clock signal.